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DATASHEET
TM TM
Programmable Rambus
General Description
XDR
Clock Generator
Features
* * * * *
ICS9220B
The ICS9220 clock generator provides Programmable clock signals to support the Rambus XDRTMmemory subsystem and Redwood logic interface. The ICS9220 has been optimized for 100MHz reference input that may or may not be modulated for spread spectrum. The ICS9220 provides 2 differential clock pairs in a space saving 28-pin TSSOP package and provides an off-the-shelf high-performance interface solution.
Figure 1 shows the major components of the ICS9220 XDR Clock Generator. These include the a PLL, a Bypass Multiplexer and two differential output buffers. The outputs can be disabled by a logic low on the OE pin. An output is enabled by the combination of the OE pin being high, and 1 * in its SMBus Output control register bit. * The PLL receives a reference clock, CLK_INT/C and outputs a clock signal at a frequency equal to the input frequency times a multiplier. Table 2 shows the multipliers selectable via the SMBus interface. This clock signal is then fed to the differential output buffers to drive the enabled clocks. Disabled outputs are set to Hi-Z. The Bypass mode routes the input clock, CLK_INT/C, directly to the differential output buffers, bypassing the PLL. Up to four ICS9220 devices can be cascaded on the same SMBus. Table 3 shows the SMBus addressing and control for the four devices.
300 - 700 MHz clock source 2 open-drain differential output drives with short term jitter < 40ps Spread spectrum compatible Reference clock is differential or single-ended 100MHz SMBus programmability for: - frequency multiplier - output enable - operating mode Support systems where XDR subsystem is asynchronous to other system clocks 2.5V power supply
Block Diagram
OE OE RegA BYPASS#/PLL
Pin Configuration
AVDD2.5 AGND IREFY AGND CLK_INT CLK_INC VDD2.5 GND SMBCLK SMBDAT OE AS1 AS2 BYPASS#/PLL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD2.5 GND GND ODCLK_T0 ODCLK_C0 GND VDD2.5 VDD2.5 GND ODCLK_T1 ODCLK_C1 GND GND VDD2.5
ODCLK_T0 ODCLK_C0
Bypass MUX
OE RegB
ODCLK_T1 ODCLK_C1
CLK_INT CLK_INC SMBCLK
PLL
SMBDAT
AS1
AS2
28-Pin 4.4mm TSSOP
IDTTM Programmable RambusTM XDRTMClock Generator 1427A--01/26/10
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ICS9220
ICS9220B Programmable RambusTM XDRTMClock Generator
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME AVDD2.5 AGND IREFY AGND CLK_INT CLK_INC VDD2.5 GND SMBCLK SMBDAT OE AS1 AS2 BYPASS#/PLL VDD2.5 GND GND ODCLK_C1 ODCLK_T1 GND VDD2.5 VDD2.5 GND ODCLK_C0 ODCLK_T0 GND GND VDD2.5 PIN TYPE PWR PWR IN PWR IN IN PWR PWR IN I/O IN IN IN IN PWR PWR PWR OUT OUT PWR PWR PWR PWR OUT OUT PWR PWR PWR DESCRIPTION 2.5V Analog Power pin for Core PLL Analog Ground pin for Core PLL This pin establishes the reference current for the differential clock pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. Analog Ground pin for Core PLL "True" reference clock input. "Complementary" reference clock input. Power supply, nominal 2.5V Ground pin. Clock pin of SMBUS circuitry, 5V tolerant Data pin of SMBUS circuitry, 5V tolerant Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Default SMBus Address Select. Default SMBus Address Select. Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode Power supply, nominal 2.5V Ground pin. Ground pin. "Complementary" side of open drain differential clock output. This open drain output needs an external resistor network.. "True" side of open drain differential clock output. This open drain output needs an external resistor network.. Ground pin. Power supply, nominal 2.5V Power supply, nominal 2.5V Ground pin. "Complementary" side of open drain differential clock output. This open drain output needs an external resistor network.. "True" side of open drain differential clock output. This open drain output needs an external resistor network.. Ground pin. Ground pin. Power supply, nominal 2.5V
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
General SMBus serial interface information for the ICS9220B How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address per table 3 ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address per table 3 ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address per table 3 ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controlle r (Host) starT bit T Slave Address table 3 WR W Rite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve/Re ce ive r)
Index Block Read Operation
T Controlle r (Host) starT bit ICS (Sla ve/Re ce ive r) Slave Address table 3 WR W Rite ACK Beginning Byte = N ACK RT Repeat starT Slave Address table 3 RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte Byte N + X - 1 N P Not acknowledge stoP bit ACK
Byte N + X - 1 ACK P stoP bit
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
I C Table: Output Enable Control Register
2
Byte 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
Pin #
-
Name
Test Mode Reserved Reserved Reserved Reserved Reserved ODCLK_T/C1 ODCLK_T/C0
Control Function
Reserved For Vendor Reserved Reserved Reserved Reserved Reserved Output Control Output Control
Type
RW RW RW RW RW RW RW RW
0
Disable Disable Disable
1
Enable Enable Enable
PWD
0 0 0 0 0 0 1 1
I C Table: Frequency Multiplier Control Register
Byte 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
Pin #
-
Name
Reserved AS1 AS2 Reserved Reserved Reserved Reserved Reserved
Control Function
Reserved SMBus Address Select SMBus Address Select Reserved Reserved Reserved Reserved Reserved
Type
R R R R R R R R
0
See Table 2 -
1
-
PWD
0 x x
-
0 0 0 0 0
I C Table: Vendor & Revision ID Register
Byte 2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
Pin #
-
Name
RID 3 RID 2 RID 1 RID 0 VID 3 VID 2 VID 1 VID 0
Control Function
Revision ID
Type
R R R R R R R R
0
-
1
-
PWD
0 0 0 0 0 0 0 1
Vendor ID
I C Table: Frequency Control Register
Byte 3
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -
Pin #
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Control Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
0 0 0 0 0 0 0 0
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
I C Table: Frequency Control Register
2
Byte 4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
Pin #
-
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Control Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
0 0 0 0 0 0 0 0
I C Table: VCO Frequency Control Register
Byte 5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -
Pin #
Name
Reserved Reserved Reserved Reserved M DIV3 M DIV2 M DIV1 M DIV0
Control Function
Reserved Reserved Reserved Reserved
Type
RW RW RW RW RW
0
-
1
-
PWD
0 0 0 0 0 0 1 0
M Divider Programming b(3:0)
RW RW RW
The decimal representation of M and N Divider in Byte 5 and 6 will configure the PLL VCO frequency. VCO frequency = 100 x {[NDIV(5:0)+2]/[MDIV(3:0)+2]}
I C Table: VCO Frequency Control Register
2
Byte 6
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -
Pin #
Name
Reserved Reserved N DIV5 N DIV4 N DIV3 N DIV2 N DIV1 N DIV0
Control Function
Type
RW RW RW
0
-
1
-
PWD
0 0 0 0 1 0 1 0
N Divider Programming b(5:0)
RW RW RW RW RW
The decimal representation of M and N Divider in Byte 5 and 6 will configure the PLL VCO frequency. VCO frequency = 100 x {[NDIV(5:0)+2]/[MDIV(3:0)+2]}
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
I C Table: Byte Count Register
2
Byte 7
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -
Pin #
Name
Control Function
Reserved Reserved Reserved
Type
0
1
PWD
0 0 0
BC4 BC3 BC2 BC1 BC0 Byte Count Programming
RW RW RW RW RW Writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes
0 0 1 1 1
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
PLL Multiplier
Table 2 shows the frequency multipliers in the PLL, selectable by programming the MULT0, MULT1 and MULT2 bits in the SMBus Multiplier Control register. Power up default is 4.
Table 2. PLL Multiplier Programming Selection M N PostDiv VCO OUTPUT B5b(3:0) B6b(5:0) B5b7 300.00000 325.00000 350.00000 366.66667 375.00000 383.33333 400.00000 416.66667 425.00000 433.33333 450.00000 466.66667 475.00000 483.33333 500.00000 516.66667 533.33333 550.00000 566.66667 583.33333 600.00000 616.66667 633.33333 4 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1200.0000 1300.0000 1400.0000 1466.6667 1500.0000 1533.3333 1600.0000 1666.6667 850.0000 866.6667 900.0000 933.3333 950.0000 966.6667 1000.0000 1033.3333 1066.6667 1100.0000 1133.3333 1166.6667 1200.0000 1233.3333 1266.6667 6 4 6 6 4 6 6 6 4 6 6 6 4 6 6 6 6 6 6 6 6 6 6 18 13 21 22 15 23 24 25 17 26 27 28 19 29 30 31 32 33 34 35 36 37 38
Byte 5 Hex 84 82 84 84 82 84 84 84 02 04 04 04 02 04 04 04 04 04 04 04 04 04 04
Byte 6 Hex 10 0B 13 14 0D 15 16 17 0F 18 19 1A 11 1B 1C 1D 1E 1F 20 21 22 23 24 25 26
4
ASIC Multiplier 6 8 1800.00 1950.00 2100.00 2200.00 2250.00 2300.00 2400.00 2500.00 2550.00 2600.00 2700.00 2800.00 2850.00 2900.00 3000.00 3100.00 3200.00 3300.00 3400.00 3500.00 3600.00 3700.00 3800.00 3900.00 4000.00 2400.00 2600.00 2800.00 2933.33 3000.00 3066.67 3200.00 3333.33 3400.00 3466.67 3600.00 3733.33 3800.00 3866.67 4000.00 4133.33 4266.67 4400.00 4533.33 4666.67 4800.00 4933.33 5066.67 5200.00 5333.33
1200.00 1300.00 1400.00 1466.67 1500.00 1533.33 1600.00 1666.67 1700.00 1733.33 1800.00 1866.67 1900.00 1933.33 2000.00 2066.67 2133.33 2200.00 2266.67 2333.33 2400.00 2466.67 2533.33 2600.00 2666.67
2 1300.0000 6 39 04 650.00000 2 1333.3333 6 40 04 666.66667 NOTE: All output values based on 100.000000MHz input clock
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
Device ID and SMBus Device Address
The device ID (SMB_A(2:1)) is part of the SMBus device address. The least significant bit of the address designates a write or read operation. Table 3 shows the addresses for four ICS9220 devices on the same SMBus.
Table 3. SMBus Device Addresses
ICS 9220
Device 0 1 2 3 Operation
Write Read Write Read Write Read Write Read
Hex Address
D8 D9 DA DB DC DD DE DF
8 bit SMBus De vice Addre ss Including Oper.
Control Function
AS2
0
AS1
0
Wr#/Rd
0 1
0 11011 1
1
0 1
0
0 1
1
1
0 1
Operating Modes
Table 4: Operating Modes Byte 1 OE BYPASS#/ PLL X X L H H H H Bit 7 Bit 1 Byte 0 ODCLK_T/C1 ODCLK_T/C0 Bit 0
L H H H H H H
X 1 0 0 0 0 0
X X X 0 0 1 1
X X X 0 1 0 1
Z
Z
Reserved for Vendor Test CLK_INT/C Z Z CLK_INT/C CLK_INT/C Z CLK_INT/C Z CLK_INT/C
Notes 1 Bypass Mode 2 Power up default mode
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
Absolute Maximum Ratings
Supply Voltage 4.0 V Logic Inputs GND -0.5 V to VDD +0.5 V Ambient Operating Temperature -40C to +85C Storage Temperature -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DC Characteristics - Outputs
TA = -40C to +85C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated) PARAMETER SYMBOL MIN TYP CONDITIONS Power within spec to outputs tPU Power up latency within spec State transition latency
1
MAX 3
UNITS ms
tCO VOX VCOS VOL, ABS VISET IOL/IREF IOL, ABS
SMBus or Mode Select transition to outputs valid and within spec Measured as shown in Fig. 3 Measured as shown in Fig. 3. Excludes over and undershoot. Measured at ODCLK_T/C pins VDD = 2.3V, VOUT = 1V IREF is equal to VISET/RRC. Tolerance of RRC <=+/-1%. Measured at ODCLK_T/C pins with termination per Figure 3. IOL = 4 mA VOL= 0.8 V 0.9 300 0.85 0.98 6.8 45 7
3 1.1 350
ms V mV V
Differential output crossing voltage Output Voltage Swing (peak-to-peak singled ended) Absolute output low voltage Reference Voltage for swing control current Ratio of output low current to reference current at typical VDD2.5 Minimum current at VOLABS
1.02 7.2 -
V mA
Low-level output voltage SMBus VOLSMB 0.4 V Low-level output current SMBus IOLSMB 6 mA Tristate output current IOZ Differential clock output pins 50 Notes: 1 There is no output latency or glitches if a value written to an output register is the same as its current contents.
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
DC Characteristics - Inputs
TA = -40C to +85C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Supply Voltage High-level input voltage Low-level input voltage Crossing point voltage Difference in crossing point voltage Input threshold voltage High-level input voltage for single-ended CLK_IN Low-level input voltage for single-ended CLK_IN High-level input voltage Low-level input voltage High-level input voltage - SMBus Low-level input voltage - SMBus VDD2.5, A VDD VIHCLK VILCLK VIXCLK VIXCLK V TH VIHSE VILSE VIH VIL VIHSMB VILSMB OE, AS1, AS2, BYPASS#/PLL SMBCLK, SMBDAT Singled-ended CLK_IN1 0.35 VTH + 0.3 -0.15 1.4 -0.15 1.4 -0.15 CLK_INT, CLK_INC 2.375 0.6 -0.15 0.2 MAX 2.625 0.95 0.15 0.55 0.15 0.5VDD2.5 2.625 VTH 0.3 2.625 0.8 3.465 0.8
2
UNITS V V V V V V V V V V V V
Notes: 1 When using singled-ended clock input, VTH is supplied to CLK_INTC as shown in Figure 2. Duty cycle of singled-ended CLK_IN is measured at VTH. 2 This range of SMBus input high voltages allows the 9220 to co-exist with 3.3V, 2.5V and 1.8V devices on the same SMBus.
AC Characteristics-Outputs
TA = -40C to +85C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated) PARAMETER
1
SYMBOL
2 tJ
Short term jitter (over 1 to 6 clock cycles) Cycle-to-cycle Jitter Duty cycle Output rise and fall times Difference between output rise and fall time on same pin of a single device Dynamic output impedance
CONDITION f = 400 to 635 MHz f = 635 to 800 MHz
MIN 45 140 1000
TYP
Tjcyc-cyc DC tR, tF tR-F ZOUT
2
20% to 80% of output voltage 20% to 80% of output voltage VOL = 0.9 V
MAX 40 30 100 55 300 100 -
UNITS ps ps ps % ps ps
Notes: 1 Guaranteed by design and characterization, not 100% tested in production 2 Zout is defined at the output pins.
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
AC Characteristics-Inputs
TA = -40C to +85C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated) PARAMETER SYMBOL CONDITION MIN TYP CLK_INT/CLK_INC cycle time Cycle-to-Cycle Jitter Input clock duty cycle CLK_INT/CLK_INC rise and fall time Difference between input rise and fall time on same pin of a single device Spread spectrum modulation frequency Spread spectrum modulation index Input clock slew rate Input Capacitance
5 5 1
MAX 11 185 60 700 150 33 0.6 0.54
UNITS ns ps % ps ps kHz % % V/ns pF pF ns kHz
t CYCLEIN t cyc -t cyc dtin t R, tF tR-F f INM3 mINDEX3 t sl(I) CINCLK CIN t CYCLETST f SMB Triangular modulation Non-triangular modulation 20% to 80% of input voltage CLK_INT, CLK_INC VI = VDD2.5 or GND Bypass Mode
2
9 over 10,000 cycles 20% to 80% of input voltage 20% to 80% of input voltage 40 175 30
10
1
4 7 10
Input Capacitance CLK_INT cycle time SMBus clock frequency
4 10
40 100
Notes: 1 Measured at (VIH(nom) - VIL(nom))/2 and is the absolute value of the worst case deviation. 2 Measured at crossing points for differential clock input or at VTH for single- ended clock input. 3 If input modulation is used. Input modulation is not necessary. 4 The amount of allowed spreading for non-triangular modulation is determined by the induced downstream tracking skew. 5 Capacitance measured at f = 1 MHz, DC bias = 0.9V, VAC <100mV.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Thermal Resistance Junction to Top of Case Maximum Case Temp
Symbol
JA JA JA JC JT
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
120 95 80 20 4.5
Max.
Units
C/W C/W C/W C/W C/W
Still Air
120
C
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
Clock Output Drivers
Figure 2 shows the clock driver equivalent circuit. The differential driver produces a specified voltage swing on the channel by switching the currents going into ODCLK_T and ODCLK_C. The external resistor RRC at the IREFY pin sets the maximum current. The minimum current is zero. The voltage at the IREFY pin, VIREFY, is by design equal to 1 V nominally, and the driver current is seven times the current flowing through RRC. So, the output low current can be estimated as IOL = 7/ RRC. The driver output characteristics are defined together with the external resistors, R1, R2, and R3. The output clock signals are specified at the measurement points indicated in Figure 2. Table 5 shows example values for the resistors. R1, R2, and R3 and the clock driver output impedance, ZOUT, must match the impedance of the channel, ZCH , to minimize secondary reflections. ZOUT is specified as 1000 Ohms, minimum to accomplish this. The effective impedance can be estimated by: (1000R1/(1000+R1)+R2) R3/(1000R1/(1000+R1)+R2+R3) Pull-up resistor RT terminates the transmission line at the load to minimize clock signal reflection signal reflections. Table 5 shows the resistor values for establishing and effective source termination impedance of 49.2 Ohms to match a 50 Ohm channel. The termination voltages are 2.5 V for VTS and 1.2 V for VT. The resistor values R1 = 38.3 Ohms, R2 = 19.1 Ohms, R3 = 54.9 Ohms and RRC = 200 Ohms can be used to match a 28 Ohm channel.
Table 5. Example Resistor Values and Termination Voltages for a 50 Ohm Channel1 Symbol R1 R2 R3 RT RRC VTS VT Parameter Termination resistor Termination resistor Termination resistor Termination resistor Swing control resistor Source termination voltage Termination voltage Value 39.2 66.5 93.1 49.9 200 2.5 1.2 Tolerance +/- 1% +/- 1% +/- 1% +/- 1% +/- 1% +/-5% +/-5% Unit V V
Notes: 1 A different set of resistors is used in Figure 2 when testing for maximum output current of the clock driver (IOLABS). These resistors are: R1 = 23, R2 = 36.5, R3 = 52.3, RT=28, RRC = 118
Supply Voltage
CLK_INC CLK_INT
VTH
Input
CLK_INT
Input
XDR Clock Generator a. Differential input
XDR Clock Generator b. Single-ended input
Figure 1. Differential and single-ended reference clock inputs
IDTTM Programmable Rambus
TM
XDR
TM
Clock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
Input Clock Signal
The ICS9220 receives either a differential or single-ended reference clock (CLK_INT/C). When the reference input clock is from a differential clock source, it must meet the voltage levels and timing requirements listed in the DC Characteristics - Inputs and AC Characteristics - Inputs tables. For a singled-ended clock input, an external voltage divider and a supply voltage, as shown in Figure 2, provide a reference voltage VTH at the CLK_INC pin to determine the proper switching point for CLK_INT. The range of VTH is specified in the DC Characteristics - Inputs table.
VTS
ODCLK_T
R1 R2 R3
Measurement Point ZCH
VT RT
Swing Current Control
ISET
Differential Driver VTS
ODCLK_C
Measurement Point ZCH
R1 R2 R3
VT RT
RRC
Figure 2. Example System Clock Driver Equivalent Circuit
VH 80% V(t) 20% VL tF tR
Figure 3. Input and Output Voltage Waveforms
ODCLK_T
Vx+ Vx,nom Vx-
ODCLK_C
Figure 4. Crossing-point Voltage
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
Power Sequencing
Supply voltages for the ICS9220 must be applied before, or at the same time and external input and output signals.
ODCLK_T
ODCLK_C
tCYCLE,i
tCYCLE,i+1
tJ = tCYCLE,i - tCYCLE, i+1 over 10,000 consecutive cycles
Figure 5. Cycle-to-cycle Jitter
ODCLK_T ODCLK_C
t4CYCLE, i
t4CYCLE, i+1
tJ = t4CYCLE, i - t4CYCLE, i+1 over 10,000 consecutive cycles
Figure 6. Short-term Jitter
ODCLK_T
Cycle (i)
Cycle (i+1)
ODCLK_C
tPW- (i) tCYCLE (i)
tPW+ (i)
tPW- (i+1) tCYCLE (i+1)
tPW+ (i+1)
tDC,ERR = tPW+(i) - tPW+(i+1) and tPW-(i) - tPW-(i+1)
Figure 7. Cycle-to-cycle Duty Cycle Error
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
N
c
4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil)
L
(25.6 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0 8 -.004
SYMBOL A A1 A2 b c D E E1 e L N a aaa VARIATIONS N
INDEX AREA
E1
E
12 D
In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0 8 -0.10
A2 A1
A
D mm. MIN 9.60 MAX 9.80 MIN .378
D (inch) MAX .386
28
-Ce
b SEATING PLANE
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
aaa C
Ordering Information
Part / Order Number Shipping Packaging Package 9220BGILF Tubes 28-pin TSSOP 9220BGILFT Tape and Reel 28-pin TSSOP Temperature -40 to +85C -40 to +85C
"LF" suffix to the part numbers are the Pb-Free configuration and are RoHS compliant. "B" is the device revision designator (will not correlate to the datasheet revision).
IDTTM Programmable RambusTM XDRTMClock Generator
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ICS9220B Programmable RambusTM XDRTMClock Generator
Revision History
Rev. 0.1 0.2 A Issue Date Description 12/10/2007 Initial release 11/9/2009 Removed "Advanced Information" banner Removed watermarks; updated ordering information; 1/26/2010 released to final Page # -
IDTTM Programmable RambusTM XDRTMClock Generator
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